Hola!
Tengo una duda con mi código.
Es un divisor binario de 4 bits, el procedimiento que hace es comprar y restar.
No me compila el programa porque dice que no puedo tener múltiples drivers. Según esto me muestra que tengo las mismos drivers en el proceso 1 y el proceso 2, pero yo no le veo algún problema. ¿Me podrían ayudar por favor?
Gracias.
Me muestra los siguientes errores:
Error (10028): Can't resolve multiple constant drivers for net "EDO.IDLE" at DIV.vhd(50)
Error (10029): Constant driver at DIV.vhd(40)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_1" at DIV.vhd(50)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_2" at DIV.vhd(50)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_3" at DIV.vhd(50)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_4" at DIV.vhd(50)
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 20 warnings
Error: Peak virtual memory: 226 megabytes
Error: Processing ended: Sat Nov 03 19:18:09 2012
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
El código
----
entity Div is
port (Dividen: unsigned(3 downto 0);
Divisor: unsigned(3 downto 0);
RST, CLK: in std_logic;
Cociente, Residuo: out std_logic_vector(3 downto 0));
end entity Div;
architecture NICE of DIV is
component SumadorRestador is
port( A,B: in std_logic_vector(7 downto 0);
Se: std_logic;
S: out std_logic_vector(7 downto 0));
end component SumadorRestador;
type EDOS is (IDLE, RES_1, RES_2, RES_3, RES_4);
signal EDO, EDOF: EDOS;
signal A,B,C,D: unsigned(3 downto 0);
signal A_1,B_1,C_1,D_1: unsigned(7 downto 0);
signal Coci: std_logic_vector(3 downto 0);
signal Ini: std_logic;
signal Dividendo: unsigned(7 downto 0);
begin
Dividendo <= "0000" & Dividen;
Ini <= RST;
p1: process(CLK,RST)
begin
if RST = '0' then
EDO <= IDLE;
elsif CLK'event and CLK='1' then
EDO <= EDOF;
end if;
end process;
p2: process (EDO, A, B, C, D, Ini, Dividendo, Divisor)
begin
case EDO is
when IDLE => if Ini = '0' then
EDO <= RES_1;
else
EDO <= IDLE;
end if;
when RES_1 => if (A > Divisor) or A = Divisor then
A_1 <= "0000" & A - Dividendo;
Coci(3) <= '1';
EDO <= RES_2;
else
A_1 <= "0000" & A;
Coci(3) <= '0';
EDO <= RES_2;
end if;
when RES_2 => if B > Divisor or B = Divisor then
B_1 <= "0000" & B - Dividendo ;
Coci(2) <= '1';
EDO <= RES_3;
else
B_1 <= "0000" & B;
Coci(2) <= '0';
EDO <= RES_3;
end if;
when RES_3 =>
if C > Divisor or C = Divisor then
C_1 <="0000" & C - Dividendo;
Coci(1) <= '1';
EDO <= RES_3;
else
C_1 <= "0000" & C;
Coci(1) <= '0';
EDO <= RES_3;
end if;
when RES_4 =>
if D > Divisor or D = Divisor then
D_1 <= "0000" & D - Dividendo;
Coci(0) <= '1';
EDO <= IDLE;
else
D_1 <= "0000" & D;
Coci(0) <= '0';
EDO <= IDLE;
end if;
when others => null;
end case;
end process;
p3: process (EDO)
begin
case EDO is
when IDLE => Cociente <= Coci;
when RES_1 => A <= Dividendo (6 downto 3);
when RES_2 => B <= A_1(2 downto 0) & Dividendo(2);
when RES_3 => C <= B_1(2 downto 0) & Dividendo(1);
when RES_4 => D <= C_1(2 downto 0) & Dividendo(0);
end case;
end process;
end architecture NICE;
Tengo una duda con mi código.
Es un divisor binario de 4 bits, el procedimiento que hace es comprar y restar.
No me compila el programa porque dice que no puedo tener múltiples drivers. Según esto me muestra que tengo las mismos drivers en el proceso 1 y el proceso 2, pero yo no le veo algún problema. ¿Me podrían ayudar por favor?
Gracias.
Me muestra los siguientes errores:
Error (10028): Can't resolve multiple constant drivers for net "EDO.IDLE" at DIV.vhd(50)
Error (10029): Constant driver at DIV.vhd(40)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_1" at DIV.vhd(50)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_2" at DIV.vhd(50)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_3" at DIV.vhd(50)
Error (10028): Can't resolve multiple constant drivers for net "EDO.RES_4" at DIV.vhd(50)
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 20 warnings
Error: Peak virtual memory: 226 megabytes
Error: Processing ended: Sat Nov 03 19:18:09 2012
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
El código
----
entity Div is
port (Dividen: unsigned(3 downto 0);
Divisor: unsigned(3 downto 0);
RST, CLK: in std_logic;
Cociente, Residuo: out std_logic_vector(3 downto 0));
end entity Div;
architecture NICE of DIV is
component SumadorRestador is
port( A,B: in std_logic_vector(7 downto 0);
Se: std_logic;
S: out std_logic_vector(7 downto 0));
end component SumadorRestador;
type EDOS is (IDLE, RES_1, RES_2, RES_3, RES_4);
signal EDO, EDOF: EDOS;
signal A,B,C,D: unsigned(3 downto 0);
signal A_1,B_1,C_1,D_1: unsigned(7 downto 0);
signal Coci: std_logic_vector(3 downto 0);
signal Ini: std_logic;
signal Dividendo: unsigned(7 downto 0);
begin
Dividendo <= "0000" & Dividen;
Ini <= RST;
p1: process(CLK,RST)
begin
if RST = '0' then
EDO <= IDLE;
elsif CLK'event and CLK='1' then
EDO <= EDOF;
end if;
end process;
p2: process (EDO, A, B, C, D, Ini, Dividendo, Divisor)
begin
case EDO is
when IDLE => if Ini = '0' then
EDO <= RES_1;
else
EDO <= IDLE;
end if;
when RES_1 => if (A > Divisor) or A = Divisor then
A_1 <= "0000" & A - Dividendo;
Coci(3) <= '1';
EDO <= RES_2;
else
A_1 <= "0000" & A;
Coci(3) <= '0';
EDO <= RES_2;
end if;
when RES_2 => if B > Divisor or B = Divisor then
B_1 <= "0000" & B - Dividendo ;
Coci(2) <= '1';
EDO <= RES_3;
else
B_1 <= "0000" & B;
Coci(2) <= '0';
EDO <= RES_3;
end if;
when RES_3 =>
if C > Divisor or C = Divisor then
C_1 <="0000" & C - Dividendo;
Coci(1) <= '1';
EDO <= RES_3;
else
C_1 <= "0000" & C;
Coci(1) <= '0';
EDO <= RES_3;
end if;
when RES_4 =>
if D > Divisor or D = Divisor then
D_1 <= "0000" & D - Dividendo;
Coci(0) <= '1';
EDO <= IDLE;
else
D_1 <= "0000" & D;
Coci(0) <= '0';
EDO <= IDLE;
end if;
when others => null;
end case;
end process;
p3: process (EDO)
begin
case EDO is
when IDLE => Cociente <= Coci;
when RES_1 => A <= Dividendo (6 downto 3);
when RES_2 => B <= A_1(2 downto 0) & Dividendo(2);
when RES_3 => C <= B_1(2 downto 0) & Dividendo(1);
when RES_4 => D <= C_1(2 downto 0) & Dividendo(0);
end case;
end process;
end architecture NICE;