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Error de VHDL durante Test Bench
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[QUOTE="Ricardotangarife, post: 1185421, member: 394998"] Realicé un programa que realiza ciertas operaciones bajo una condiciones y un selector; funciona bien. El problema es cuando realizo el Test Bench automatizado para este; las variables de comparación al realizar la simulación tiene un desfase temporal; entonces al realizar la comparación las dos señales se encuentran en diferente estado y la comparación es fallida; quiero saber si alguien puede saber cómo arreglarlo; las salidas en comparación son STT y Salida2: Programa Principal [code]---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04.09.2017 11:28:51 -- Design Name: -- Module Name: pract3 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use STD.textio.all; use IEEE.std_logic_textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity pract3 is Port ( FB0 : in STD_LOGIC_VECTOR(3 downto 0); FB1 : in STD_LOGIC_VECTOR(3 downto 0); FA0 : in STD_LOGIC_VECTOR(3 downto 0); FuenteB : in STD_LOGIC; D : in STD_LOGIC_VECTOR(2 downto 0); MA : out STD_LOGIC; MB : out STD_LOGIC; C : out STD_LOGIC; An : out STD_LOGIC_VECTOR(3 downto 0); S : out STD_LOGIC_VECTOR(6 downto 0) ); end pract3; architecture Behavioral of pract3 is signal FB : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal MAt : STD_LOGIC:=\'0\'; signal MBt : STD_LOGIC:=\'0\'; signal Ct : STD_LOGIC:=\'0\'; signal Ant : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal St : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal Sti : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal Salidat : STD_LOGIC_VECTOR(6 downto 0):="0000000"; signal suma : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal sumat : STD_LOGIC_VECTOR(4 downto 0):="00000"; signal max : STD_LOGIC_VECTOR(4 downto 0):="01111"; signal stte : STD_LOGIC_VECTOR(4 downto 0):="00000"; signal stt1 : STD_LOGIC_VECTOR(4 downto 0):="00000"; signal stt2 : STD_LOGIC_VECTOR(4 downto 0):="00000"; begin --Proceso de seleccion de entrada al bus B selc: process(FB0,FB1,FuenteB) begin case FuenteB is when \'0\' => FB <= FB1; when \'1\' => FB <= FB0; when others => FB <= "ZZZZ"; end case; end process; --Selección de bus mayor comp: process(FA0,FB) begin if(FA0<FB) then MB <= \'1\'; --MBt MA <= \'0\'; --MAt else MB <= \'0\'; --MBt MA <= \'1\'; --MAt end if; end process; -- SUMA DE LOS DATOS DE ENTRADA stt1 <= \'0\'&FA0; stt2 <= \'0\'&FB; sumat <= stt1+stt2; process(sumat) begin stte <= sumat-max; if sumat > max then C <= \'1\'; suma <= stte(3 downto 0); else C <= \'0\'; suma <= sumat(3 downto 0); end if ; end process; -- Realizador de operaciones oper: process(FA0,D,FB,suma) begin case D is when "000" => An <= "1110"; St <= FA0 XOR FB; when "001" => An <= "1110"; St <= suma; when "010" => An <= "1110"; St <= FA0 XNOR FB; when "011" => An <= "1110"; St <= FA0 AND FB; when "100" => An <= "1101"; St <= FB; when "101" => An <= "1011"; St <= FA0; when "110" => An <= "0000"; St <= "0000"; when "111" => An <= "0000"; St <= "1111"; when others => St <= "ZZZZ"; end case; end process; --Despliegue en el diplay with St select--se asigna el valor a display segun que segmentos debe encender con un decodificador Salidat <= "0000001" when "0000", "1001111" when "0001", "0010010" when "0010", "0000110" when "0011", "1001100" when "0100", "0100100" when "0101", "0100000" when "0110", "0001111" when "0111", "0000000" when "1000", "0000100" when "1001", "0001000" when "1010", "1100000" when "1011", "0110001" when "1100", "1000010" when "1101", "0010000" when "1110", "0111000" when "1111", "ZZZZZZZ" WHEN others; S <= Salidat; end Behavioral; [/code] Test Bench: [code]---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11.09.2017 11:11:55 -- Design Name: -- Module Name: pract3_tb - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use STD.textio.all; use IEEE.std_logic_textio.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity pract3_tb is end pract3_tb; architecture Behavioral of pract3_tb is component pract3 port( FB0 : in STD_LOGIC_VECTOR(3 downto 0); FB1 : in STD_LOGIC_VECTOR(3 downto 0); FA0 : in STD_LOGIC_VECTOR(3 downto 0); FuenteB : in STD_LOGIC; D : in STD_LOGIC_VECTOR(2 downto 0); MA : out STD_LOGIC; MB : out STD_LOGIC; C : out STD_LOGIC; An : out STD_LOGIC_VECTOR(3 downto 0); S : out STD_LOGIC_VECTOR(6 downto 0) ); end component; signal FB0TT : STD_LOGIC_VECTOR(3 downto 0):="0000";-- signal FB1TT : STD_LOGIC_VECTOR(3 downto 0):="0000";-- signal FBB : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal FA0TT : STD_LOGIC_VECTOR(3 downto 0):="0000";-- signal FuenteBTT : STD_LOGIC:=\'0\';-- signal DTT : STD_LOGIC_VECTOR(2 downto 0):="000";-- signal MATT : STD_LOGIC:=\'0\'; signal MBTT : STD_LOGIC:=\'0\'; signal CTT : STD_LOGIC:=\'0\'; signal CTTP : STD_LOGIC:=\'0\'; signal AnTT : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal AnTTP : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal STT : STD_LOGIC_VECTOR(6 downto 0):="0000000";-- signal Sst : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal STB : STD_LOGIC_VECTOR(6 downto 0):="0000000"; signal sumas : STD_LOGIC_VECTOR(3 downto 0):="0000"; signal max : STD_LOGIC_VECTOR(3 downto 0):="1111"; signal Salida2 : STD_LOGIC_VECTOR(6 downto 0):="0000000"; signal wha : STD_LOGIC:=\'0\'; begin DUT: pract3 PORT MAP( FB0 => FB0TT, FB1 => FB1TT, FA0 => FA0TT, FuenteB => FuenteBTT, D => DTT, MA => MATT, MB => MBTT, C => CTT, An => AnTT, S => STT ); process variable i : integer :=0; variable j : integer :=0; variable k : integer :=0; variable l : integer :=0; variable linea : line; variable at : STD_LOGIC_VECTOR(4 downto 0):="00000"; variable bt : STD_LOGIC_VECTOR(4 downto 0):="00000"; variable sumaabt : STD_LOGIC_VECTOR(4 downto 0):="00000"; variable restabt : STD_LOGIC_VECTOR(4 downto 0):="00000"; begin for i in 0 to 1 loop for j in 0 to 15 loop for k in 0 to 15 loop for l in 0 to 7 loop if(i=0)then FBB <= FB1TT; else FBB <= FB0TT; end if; at := \'0\'&FA0TT; bt := \'0\'&FBB; sumaabt := at+bt; restabt := at-max; if sumaabt > max then CTTP <= \'1\'; sumas <= restabt(3 downto 0); else CTTP <= \'0\'; sumas <= sumaabt(3 downto 0); end if ; case DTT is when "000" => AnTTP <= "1110"; Sst <= FA0TT XOR FBB; when "001" => AnTTP <= "1110"; Sst <= sumas; when "010" => AnTTP <= "1110"; Sst <= FA0TT XNOR FBB; when "011" => AnTTP <= "1110"; Sst <= FA0TT AND FBB; when "100" => AnTTP <= "1101"; Sst <= FBB; when "101" => AnTTP <= "1011"; Sst <= FA0TT; when "110" => AnTTP <= "0000"; Sst <= "0000"; when "111" => AnTTP <= "0000"; Sst <= "1111"; when others => Sst <= "ZZZZ"; end case; case Sst is when "0000" => Salida2 <= "0000001"; when "0001" => Salida2 <= "1001111"; when "0010" => Salida2 <= "0010010"; when "0011" => Salida2 <= "0000110"; when "0100" => Salida2 <= "1001100"; when "0101" => Salida2 <= "0100100"; when "0110" => Salida2 <= "0100000"; when "0111" => Salida2 <= "0001110"; when "1000" => Salida2 <= "0000000"; when "1001" => Salida2 <= "0001100"; when "1010" => Salida2 <= "0001000"; when "1011" => Salida2 <= "1100000"; when "1100" => Salida2 <= "0110001"; when "1101" => Salida2 <= "1000010"; when "1110" => Salida2 <= "0110000"; when "1111" => Salida2 <= "0111000"; when others => Salida2 <= "ZZZZZZZ"; end case; if(Salida2=STT)then write(linea,string\'("El proceso es correcto")); writeline(output, linea); wha <= \'1\'; else write(linea,string\'("El proceso es incorrecto")); writeline(output, linea); wha <= \'0\'; end if; wait for 20 ns; DTT <= DTT+1; end loop; FA0TT <= FA0TT+1; end loop; FB0TT <= FB0TT+1; FB1TT <= FB1TT+1; end loop; FuenteBTT <= \'1\'; end loop; end process; end Behavioral;[/code] Cuando realizo la simulación; se ve el desfase entre las señales comparadas, Muchas Gracias ... [/QUOTE]
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