Library ieee;
use ieee.std_logic_1164.all;
entity FFD_8 is
port(
oe,clk : in std_logic;
data_in : in std_logic_vector (7 downto 0);-- in D
data_out: out std_logic_vector (7 downto 0)-- out Q
);
end FFD_8;
Architecture func of FFD_8 is
begin
process(clk,oe)
begin
if (oe ='0') then-- output enable
data_out <= "ZZZZZZZZ";
elsif(clk' event and clk='1') then-- esto detecta las transiciones de subida
data_out <= data_in;
end if;
end process;
end func;