implementacion de process vhdl

tckjonixx · May 10, 2012

que pena compañeros mi pregunta es podria implementar un process en la parte del codigo

Código:

   num <= "0001" when count=0 and F1='1' else
     "0010" when count=1 and F1='1' else 
     "0011" when count=2 and F1='1' else 
     "0100" when count=0 and F2='1' else 
     "0101" when count=1 and F2='1' else 
     "0110" when count=2 and F2='1' else 
     "0111" when count=0 and F2='1' else 
     "1000" when count=0 and F3='1' else 
     "1001" when count=1 and F3='1' else 
     "0000" WHEN COUNT=2 AND F3='1' ELSE
     "1010" when count=0 and F4='1' else 
     "1011" when count=1 and F4='1' else 
     "1100" when count=2 and F4='1' ;

este es mi codogo (lo q intento hacer es mostrar en la lcd de la spartan lo que uno digita en un teclado matricial

Código:

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:45:02 05/04/2012 
-- Design Name: 
-- Module Name:    four_four - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity four_four is
GENERIC(CLK_DIVIDE:INTEGER:=50000);
    Port ( clk,rest : in  STD_LOGIC;
           F1,F2,F3,F4 : in  STD_LOGIC;
           C1,C2,C3 : inout  STD_LOGIC;
			  RST: 	IN BIT;
           RS,RW,SF_CEO: out BIT;
			  E:BUFFER BIT;
			  DB:out BIT_VECTOR(3 downto 0));
end four_four;

architecture Behavioral of four_four is
signal count:std_logic_vector (1 downto 0);
TYPE Estados IS (F_INIT_1A,F_INIT_1B,F_INIT_2A,
F_INIT_2B,F_INIT_3A,F_INIT_3B,BORRAR1,BORRAR2,
Control1,Control2,Modo1,Modo2,M1,M2,R3,R4);
SIGNAL pr_estado, nx_estado:Estados;
signal   nBL :   STD_LOGIC;

signal num : BIT_VECTOR(3 downto 0); 
begin
nbl<=F1 or F2 OR F3 or F4;
--- contador activar columnas
p1:process (clk,rest)
begin
if (rest='1') then
count <=(others => '0');
elsif(clk'event and clk='1') then
if (count < 2) then 
count<=count+1;
else
count <=(others => '0');
end if;
end if;
end process;

--activacion de las colum
C1<= '1' when count=0 else '0';
C2<= '1' when count=1 else '0';
C3<= '1' when count=2 else '0';
--- a la lcd

   num <= "0001" when count=0 and F1='1' else
     "0010" when count=1 and F1='1' else 
     "0011" when count=2 and F1='1' else 
     "0100" when count=0 and F2='1' else 
     "0101" when count=1 and F2='1' else 
     "0110" when count=2 and F2='1' else 
     "0111" when count=0 and F2='1' else 
     "1000" when count=0 and F3='1' else 
     "1001" when count=1 and F3='1' else 
     "0000" WHEN COUNT=2 AND F3='1' ELSE
     "1010" when count=0 and F4='1' else 
     "1011" when count=1 and F4='1' else 
     "1100" when count=2 and F4='1' ; 

------------------------------------------------------------------
---------------lcd inicializacion (proceso)---------------------------------
------------------------------------------------------------------

SF_CEO<='1';
RELOJ_500Hz: PROCESS(CLK)

VARIABLE Cuenta: INTEGER RANGE 0 TO CLK_DIVIDE;
 begin
       IF(CLK'EVENT AND CLK='1')THEN
		    Cuenta:=Cuenta+1;
			 IF(Cuenta=CLK_DIVIDE)THEN
			    E<=NOT E;
			 END IF;
		 END IF;
   END PROCESS;
MAQUINA: PROCESS(E)
BEGIN
   IF(E'EVENT AND E='1')THEN
	   IF(RST='1')THEN
		  pr_estado<=F_INIT_1A;
		ELSE
		  pr_estado<=nx_estado;
	   END IF;
	END IF;
END PROCESS;

FSM: PROCESS(pr_estado)
    BEGIN
	   CASE pr_estado IS
		   WHEN F_INIT_1A =>
			    RS<='0';RW<='0';
				 DB<="0010";
				 nx_estado<=F_INIT_1B;
			WHEN F_INIT_1B =>
			    RS<='0';RW<='0';
		       DB<="1000";
			    nx_estado<=F_INIT_2A;
			WHEN F_INIT_2A =>
			    RS<='0';RW<='0';
		       DB<="0010";
			    nx_estado<=F_INIT_2B;
			WHEN F_INIT_2B =>
			    RS<='0';RW<='0';
		       DB<="1000";
			    nx_estado<=F_INIT_3A;
			WHEN F_INIT_3A =>
			    RS<='0';RW<='0';
		       DB<="0010";
			    nx_estado<=F_INIT_3B;
			WHEN F_INIT_3B =>
			    RS<='0';RW<='0';
		       DB<="1000";
			    nx_estado<=BORRAR1;
----------------------------------------------------------------------------------
			WHEN BORRAR1 =>
			    RS<='0';RW<='0';
		       DB<="0000";
			    nx_estado<=BORRAR2;
			WHEN BORRAR2 =>
			    RS<='0';RW<='0';
		       DB<="0001";
			    nx_estado<=Control1;
----------------------------------------------------------------------------------
			WHEN Control1 =>
			    RS<='0';RW<='0';
		       DB<="0000";
			    nx_estado<=Control2;
			WHEN Control2 =>
			    RS<='0';RW<='0';
		       DB<="1100";
			    nx_estado<=Modo1;
----------------------------------------------------------------------------------
         WHEN Modo1 =>
			    RS<='0';RW<='0';
		       DB<="0000";
			    nx_estado<=Modo2;
			WHEN Modo2 =>
			    RS<='0';RW<='0';
		       DB<="0110";
			    nx_estado<=M1;
--------------------------------------------------------------------------------
         WHEN M1 =>
			    RS<='1';RW<='0';
		       DB<="0011";
			    nx_estado<=M2;
			WHEN M2 =>
			    RS<='1';RW<='0';
		       DB<=num;
			    nx_estado<=R3;

--------------------------------------------------------------------------------

		  WHEN R3 =>
			    RS<='0';RW<='0';
		       DB<="1000";
			    nx_estado<=R4;
			WHEN R4 =>
			    RS<='0';RW<='0';
		       DB<="0000";
			    nx_estado<=R3;				 
  END CASE;
END PROCESS;

end Behavioral;

implementacion de process vhdl

tckjonixx

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