Hola a to2
En la u estamos me mandaron un proyecto en el cual me toca manejar potenciómetros digitales y los único que encontré en mi zona fue el MCP42xxx
pero soy nuevo con ellos y no sé cómo se manejan, y el data no lo entiendo mucho, alguno de uds me podrían ayudar a ver cómo manejarlos les agradecería
Estos son los pines de control gx:
3.0 PIN DESCRIPTIONS
3.1 PA0, PA1
Potentiometer Terminal A Connection.
3.2 PB0, PB1
Potentiometer Terminal B Connection.
3.3 PW0, PW1
Potentiometer Wiper Connection.
3.4 Chip Select (CS)
This is the SPI port chip select pin and is used to execute
a new command after it has been loaded into the
shift register. This pin has a Schmitt Trigger input.
3.5 Serial Clock (SCK)
This is the SPI port clock pin and is used to clock-in
new register data. Data is clocked into the SI pin on the
rising edge of the clock and out the SO pin on the falling
edge of the clock. This pin is gated to the CS pin (i.e.,
the device will not draw any more current if the SCK pin
is toggling when the CS pin is high). This pin has a
Schmitt Trigger input.
3.6 Serial Data Input (SI)
This is the SPI port serial data input pin. The command
and data bytes are clocked into the shift register using
this pin. This pin is gated to the CS pin (i.e., the device
will not draw any more current if the SI pin is toggling
when the CS pin is high). This pin has a Schmitt Trigger
input.
3.7 Serial Data Output (SO)
(MCP42XXX devices only)
This is the SPI port serial data output pin used for
daisy-chaining more than one device. Data is clocked
out of the SO pin on the falling edge of clock. This is a
push-pull output and does not go to a high-impedance
state when CS is high. It will drive a logic-low when CS
is high.
3.8 Reset (RS)
(MCP42XXX devices only)
The Reset pin will set all potentiometers to mid-scale
(Code 80h) if this pin is brought low for at least 150 ns.
This pin should not be toggled low when the CS pin is
low. It is possible to toggle this pin when the SHDN pin
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negligible
current at logic level ‘0’ and logic level ‘1’. Do not
leave this pin floating.
En la u estamos me mandaron un proyecto en el cual me toca manejar potenciómetros digitales y los único que encontré en mi zona fue el MCP42xxx
pero soy nuevo con ellos y no sé cómo se manejan, y el data no lo entiendo mucho, alguno de uds me podrían ayudar a ver cómo manejarlos les agradecería
Estos son los pines de control gx:
3.0 PIN DESCRIPTIONS
3.1 PA0, PA1
Potentiometer Terminal A Connection.
3.2 PB0, PB1
Potentiometer Terminal B Connection.
3.3 PW0, PW1
Potentiometer Wiper Connection.
3.4 Chip Select (CS)
This is the SPI port chip select pin and is used to execute
a new command after it has been loaded into the
shift register. This pin has a Schmitt Trigger input.
3.5 Serial Clock (SCK)
This is the SPI port clock pin and is used to clock-in
new register data. Data is clocked into the SI pin on the
rising edge of the clock and out the SO pin on the falling
edge of the clock. This pin is gated to the CS pin (i.e.,
the device will not draw any more current if the SCK pin
is toggling when the CS pin is high). This pin has a
Schmitt Trigger input.
3.6 Serial Data Input (SI)
This is the SPI port serial data input pin. The command
and data bytes are clocked into the shift register using
this pin. This pin is gated to the CS pin (i.e., the device
will not draw any more current if the SI pin is toggling
when the CS pin is high). This pin has a Schmitt Trigger
input.
3.7 Serial Data Output (SO)
(MCP42XXX devices only)
This is the SPI port serial data output pin used for
daisy-chaining more than one device. Data is clocked
out of the SO pin on the falling edge of clock. This is a
push-pull output and does not go to a high-impedance
state when CS is high. It will drive a logic-low when CS
is high.
3.8 Reset (RS)
(MCP42XXX devices only)
The Reset pin will set all potentiometers to mid-scale
(Code 80h) if this pin is brought low for at least 150 ns.
This pin should not be toggled low when the CS pin is
low. It is possible to toggle this pin when the SHDN pin
is low. In order to minimize power consumption, this pin
has an active pull-up circuit. The performance of this
circuit is shown in Figure 2-12. This pin will draw negligible
current at logic level ‘0’ and logic level ‘1’. Do not
leave this pin floating.
