aqui te dejo un ejemplo mas completo es una comunicacion por serial a 9600 baud
;*******************************************************************
;* This stationery serves as the framework for a user application. *
;* For a more comprehensive program that demonstrates the more *
;* advanced functionality of this processor, please see the *
;* demonstration applications, located in the examples *
;* subdirectory of the "Freescale CodeWarrior for HC08" program *
;* directory. *
;*******************************************************************
; Include derivative-specific definitions
INCLUDE 'derivative.inc'
XREF MCU_init
; export symbols
XDEF _Startup, main
; we export both '_Startup' and 'main' as symbols. Either can
; be referenced in the linker .prm file or from C/C++ later on
XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack
; variable/data section
MY_ZEROPAGE: SECTION SHORT ; Insert here your data definition
; code section
MyCode: SECTION
main:
_Startup:
LDHX #__SEG_END_SSTACK ; initialize the stack pointer
TXS
; Call generated Device Initialization function
JSR MCU_init
CLI ; enable interrupts
mainLoop:
; Insert your code here
bset 3,PTD
NOP
BCLR 3,PTD
NOP
bset 3,PTD
NOP
BCLR 3,PTD
NOP
;JSR TX_OK
feed_watchdog
BRA mainLoop
;//////////////////////////////////////////////////////////////////////////////
TX_OK:
LDA #'H' ;#$48 letra H
STA SCDR
X1: STA COPCTL ; Reset watchdog counter
brclr 7,SCS1,X1 ; ESPERA HASTA QUE TERMINE LA TRANSMISION
LDA #'O' ;#$4f letra o
STA SCDR
X2: STA COPCTL ; Reset watchdog counter
brclr 7,SCS1,X2 ; ESPERA HASTA QUE TERMINE LA TRANSMISION
LDA #'L' ;#$4C letra L
STA SCDR
X3: STA COPCTL ; Reset watchdog counter
brclr 7,SCS1,X3 ; ESPERA HASTA QUE TERMINE LA TRANSMISION
LDA #'A' ;#$40 letra @
STA SCDR
X4: STA COPCTL ; Reset watchdog counter
brclr 7,SCS1,X4 ; ESPERA HASTA QUE TERMINE LA TRANSMISION
LDA #$0D
STA SCDR
X5: STA COPCTL ; Reset watchdog counter
brclr 7,SCS1,X5 ; ESPERA HASTA QUE TERMINE LA TRANSMISION
RTS
;//////////////////////////////////////////////////////////////////////////////
;** ###################################################################
;** This code is generated by the Device Initialization Tool.
;** It is overwritten during code generation.
;** USER MODIFICATION ARE PRESERVED ONLY INSIDE INTERRUPT SERVICE ROUTINES
;** OR EXPLICITLY MARKED SECTIONS
;**
;** Project : PRUEBA_SERIAL_AP16_9600
;** Processor : MC68HC908AP16CB
;** Version : Bean 01.083, Driver 01.00, CPU db: 2.89.096
;** Datasheet : MC68HC908AP64 Rev. 3 8/2005 / MC68HC908AP64A Rev. 1 3/2005
;** Date/Time : 25/03/2010, 03:17 p.m.
;** Abstract :
;** This bean "MC68HC908AP64_42" provides initialization of the
;** CPU core and shared peripherals.
;** Settings :
;** Clock setting
;** External clock : 9.8304 MHz
;** Internal clock : 88 kHz
;** CPU mode selection : 0
;** Initialization interrupt priority : 1
;** Stop instruction enabled : no
;** LVI module : Enabled
;**
;** Source clock : External Clock
;** Internal bus clock : 2.4576 MHz
;** Contents :
;** Function "MCU_init" initializes selected peripherals
;**
;** (c) Copyright UNIS, spol. s r.o. 1997-2006
;** UNIS, spol s r.o.
;** Jundrovska 33
;** 624 00 Brno
;** Czech Republic
;** http :
www.processorexpert.com
;** mail :
info@processorexpert.com
;** ###################################################################
; MODULE MCUinit
INCLUDE MC68HC908AP64.inc ; I/O map for MC68HC908AP16CB
; User declarations and definitions
; Code, declarations and definitions here will be preserved during code generation
; End of user declarations and definitions
CGM_DELAY: EQU $27FF
CODE_SECT: SECTION
XDEF MCU_init
;** ===================================================================
;** Method : MCU_init (bean MC68HC908AP64_42)
;**
;** Description :
;** Device initialization code for selected peripherals.
;** ===================================================================
MCU_init:
;** ### MC68HC908AP64_42 "Cpu" init code ... **
;** PE initialization code after reset **
; System clock initialization
; Common initialization of the write once registers
; CONFIG1: COPRS=0,LVISTOP=0,LVIRSTD=0,LVIPWRD=0,LVIREGD=0,SSREC=0,STOP=0,COPD=1
MOV #$01,CONFIG1
; CONFIG2: STOP_ICLKDIS=0,STOP_RCLKEN=0,STOP_XCLKEN=0,OSCCLK1=0,OSCCLK0=0,SCIBDSRC=1
MOV #$01,CONFIG2
; Common initialization of the CPU registers
; ### Init_SCI init code
; SCC1: LOOPS=0,ENSCI=0,TXINV=0,M=0,WAKE=0,ILTY=0,PEN=0,PTY=0
CLR SCC1 ; Disable the SCI module
LDA SCS1 ; Dummy read of the SCS1 registr to clear flags
LDA SCS2 ; Dummy read of the SCS2 registr to clear flags
LDA SCDR ; Dummy read of the SCDR registr to clear flags
; SCC3: R8=0,T8=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0
CLR SCC3
; SCBR: SCP1=0,SCP0=0,SCR2=0,SCR1=1,SCR0=0
MOV #$02,SCBR
; SCC1: LOOPS=0,ENSCI=1,TXINV=0,M=0,WAKE=0,ILTY=0,PEN=0,PTY=0
MOV #$40,SCC1
; SCC2: SCTIE=0,TCIE=0,SCRIE=0,ILIE=0,TE=1,RE=0,RWU=0,SBK=0
MOV #$08,SCC2
; ### Init_KBI init code
; KBSCR: IMASK=1
BSET $01,KBSCR
; KBIER: KBIE7=0,KBIE6=0,KBIE5=0,KBIE4=0,KBIE3=0,KBIE2=0,KBIE1=0,KBIE0=1
MOV #$01,KBIER
; KBSCR: MODE=0
BCLR $00,KBSCR
; KBSCR: ACK=1
BSET $02,KBSCR
; KBSCR: IMASK=0
BCLR $01,KBSCR
; ### Init_GPIO init code
; DDRD: DDRD3=1
BSET $03,DDRD
; ###
CLI ; Enable interrupts
RTS
;** ===================================================================
;** Interrupt handler : isrINT_KBD
;**
;** Description :
;** User interrupt service routine.
;** Parameters : None
;** Returns : Nothing
;** ===================================================================
XDEF isrINT_KBD
isrINT_KBD:
; Write your interrupt code here ...
RTI
; end of isrINT_KBD
;** ===================================================================
;** Interrupt handler : isrINT_SCITransmit
;**
;** Description :
;** User interrupt service routine.
;** Parameters : None
;** Returns : Nothing
;** ===================================================================
XDEF isrINT_SCITransmit
isrINT_SCITransmit:
; Write your interrupt code here ...
RTI
; end of isrINT_SCITransmit
;** ===================================================================
;** Interrupt handler : isrINT_SCIReceive
;**
;** Description :
;** User interrupt service routine.
;** Parameters : None
;** Returns : Nothing
;** ===================================================================
XDEF isrINT_SCIReceive
isrINT_SCIReceive:
; Write your interrupt code here ...
RTI
; end of isrINT_SCIReceive
;** ===================================================================
;** Interrupt handler : isrINT_SCIError
;**
;** Description :
;** User interrupt service routine.
;** Parameters : None
;** Returns : Nothing
;** ===================================================================
XDEF isrINT_SCIError
isrINT_SCIError:
; Write your interrupt code here ...
RTI
; end of isrINT_SCIError
; Initialization of the CPU registers in FLASH
; MOR: OSCSEL1=1,OSCSEL0=1
ORG MOR
DC.B $FF
ifndef UNASSIGNED_ISR
UNASSIGNED_ISR: EQU $FFFF ; unassigned interrupt service routine
endif
XREF _Startup ; reset interrupt service routine
ORG $FFD2 ; Interrupt vector table
_vect:
DC.W UNASSIGNED_ISR ; Int.no. 0 INT_TBM (at FFD2) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 1 INT_IRSCITransmit (at FFD4) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 2 INT_IRSCIReceive (at FFD6) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 3 INT_IRSCIError (at FFD8) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 4 INT_SPITransmit (at FFDA) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 5 INT_SPIReceive (at FFDC) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 6 INT_ADC (at FFDE) Unassigned
DC.W isrINT_KBD ; Int.no. 7 INT_KBD (at FFE0) Used
DC.W isrINT_SCITransmit ; Int.no. 8 INT_SCITransmit (at FFE2) Used
DC.W isrINT_SCIReceive ; Int.no. 9 INT_SCIReceive (at FFE4) Used
DC.W isrINT_SCIError ; Int.no. 10 INT_SCIError (at FFE6) Used
DC.W UNASSIGNED_ISR ; Int.no. 11 INT_MMIIC (at FFE8) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 12 INT_TIM2Ovr (at FFEA) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 13 INT_TIM2CH1 (at FFEC) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 14 INT_TIM2CH0 (at FFEE) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 15 INT_TIM1Ovr (at FFF0) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 16 INT_TIM1CH1 (at FFF2) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 17 INT_TIM1CH0 (at FFF4) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 18 INT_PLL (at FFF6) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 19 Reserved19 (at FFF8) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 20 INT_IRQ1 (at FFFA) Unassigned
DC.W UNASSIGNED_ISR ; Int.no. 21 INT_SWI (at FFFC) Unassigned
DC.W _Startup ; Int.no. 22 INT_RESET (at FFFE) Reset vector
END ; MODULE MCUinit
;** ###################################################################
;**
;** This file was created by UNIS Processor Expert 3.01 [03.92]
;** for the Freescale HC08 series of microcontrollers.
;**
;** ###################################################################
Muchas gracias. Saludos!!
