Hola, estaba realizando el Proyecto de una ALU, pero la verdad, no sé que componentes crear para poder operar, elegir y visualizar las entradas y salidas correspondientes a los procesos realizados por la ALU en la FPGA ya que nunca he usado una...
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ALU is
port
(
sel :in std_logic_vector(2 downto 0);
A,B :in std_logic_vector(15 downto 0);
result: out std_logic_vector(16 downto 0)
);
end ALU;
architecture ARCHYUNITEU of ALU is
begin
process (sell, A, B) is
begin
case sel is
when "000" =>
result<= ('0' & A) OR B;
when "001" =>
result<= ('0' & A) AND B;
when "010" =>
result<= NOT ('0'& A);
when "011" =>
result<= ('0' & A) ;
when "100" =>
result<= ('0'& A) + B;
when "101" =>
result<= ('0' & A) - B;
when "110" =>
result<= (('0'&A) + 1);
when others =>
result<= (('0'&A) - 1);
end case;
end process;
end ARCHYUNITEU;
Muchas Gracias
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ALU is
port
(
sel :in std_logic_vector(2 downto 0);
A,B :in std_logic_vector(15 downto 0);
result: out std_logic_vector(16 downto 0)
);
end ALU;
architecture ARCHYUNITEU of ALU is
begin
process (sell, A, B) is
begin
case sel is
when "000" =>
result<= ('0' & A) OR B;
when "001" =>
result<= ('0' & A) AND B;
when "010" =>
result<= NOT ('0'& A);
when "011" =>
result<= ('0' & A) ;
when "100" =>
result<= ('0'& A) + B;
when "101" =>
result<= ('0' & A) - B;
when "110" =>
result<= (('0'&A) + 1);
when others =>
result<= (('0'&A) - 1);
end case;
end process;
end ARCHYUNITEU;
Muchas Gracias