hola
gracias a todos por responder y por la ayuda.La placa aun no la he montado,solo tengo el esquema que me paso mi amigo y a la hora de comprar los componentes,este problema me encontre con las memorias.En el datasheet del micro especifica lo siguiente:
The SDRAMC supports the following:
• Optimization of consecutive memory accesses using memory command anticipation (latency
hiding)
— Hiding latency (or “command anticipation”) by optimizing the commands to both connected
chip-selects
— Monitoring open memory pages
— Bank-wise memory address mapping
— SDRAM burst length configuration of 41 or 8 bursts or full-page mode
— MDDR burst length configuration of 8 bursts
— Support of different internal burst length (1/4/8 words) by using burst truncate commands
— ARM/AMBA/AHB-Lite compliant
— Shared address and command bus to SDRAM/MDDR
• Supports 64, 128, 256, 512 Mbit, 1 Gbit, and 2 Gbit, 4 bank, single data rate, synchronous
SDRAM, and MDDR
— Two independent chip-selects
— Up to 128 Mbytes per chip-select
— Up to four banks active simultaneously per chip-select
— JEDEC standard pinout/operation
• Supports mobile DDR266 devices (both 16-bit and 32-bit)
• PC133 compliant interface
— 133-MHz system clock achievable with “–7” option PC133 compliant memories
— Single fixed-length (4/8-word) burst or full page access
— Access time of 9-1-1-1-1-1-1-1 at 133 MHz (for read access when the memory bus is available,
the row is open and CAS latency configured to three cycles). The access time includes the
M3IF delay (assuming there is no arbitration penalty).
• Software configurable for different system and memory devices requirements
— 16-bit or 32-bit memory data bus width
— Many row and column addresses
— Row cycle delay (tRC)
— Row precharge delay (tRP)
— Row-to-column delay (tRCD)
— Column-to-data delay (CAS latency)
— Load mode register to active command (tMRD)
— Write to precharge (tWR)
— Write to read (tWTR) for MDDR memories only
— MDDR exit power down to next valid command delay (tXS)
— Active to precharge (tRAS)
— Active to active (tRRD)
• Built-in auto-refresh timer and state machine
• Hardware and software supported self-refresh entry and exit
— Keeps data valid during system reset and low-power modes
— Auto Power Down timer (one per chip-select)
— Auto Precharge timer (one per bank in each chip-select)
Muchas gracias por la ayuda,yo es que de memorias lo justito,en su dia 8051 y no habia que mirar tanto y con los pic, como va todo dentro jejeje. muchas gracias.
saludos